Massively Parallel Programming with CUDA -- JUST ADDED

Wednesday, July 23 | 12:15 PM–1:15 PM

Tim Murray, Applied Engineer, Tesla/CUDA products, NVIDIA

As the number of cores available on microprocessors increases, data-parallel languages -- where parallelism is expressed in terms of data rather than tasks -- will inevitably become the preferred programming model for many applications. NVIDIA's CUDA provides a set of data-parallel extensions to C that let applications run on a Graphics Processing Unit (GPU) – a massively parallel processor capable of up to one teraflop. By expressing parallelism this way, programmers can create tens of millions of threads and maximize the computational power available both on current and future hardware. This presentation will cover a brief history of data-parallel processing, provide an overview of the CUDA execution model, the teraflop-capable Tesla 10 series GPU, and examine how applications can take advantage of CUDA facilities.

Tim Murray: A recent graduate from Carnegie Mellon University with a BS in computer science, Tim is one of the newest members of the applied engineering team in the Computing group at NVIDIA. At University, Tim's focus was on robotics, including the development of a distributed system for robot planning and control. As a part-time freelancer for the well respected technology site, Beyond3D, he attended an Editors Day at NVIDIA in 2007 on the subject of CUDA and was hooked from there. His current research areas include accelerating artificial intelligence, machine learning and computational finance on the GPU leveraging CUDA.

 
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